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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\TangPrimer-25K-example\pmod_lcd\impl\gwsynthesis\pmod_lcd.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\TangPrimer-25K-example\pmod_lcd\src\pmod_lcd.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-3</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Aug 24 18:18:39 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.85V -40C ES</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 0.95V 100C ES</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>224</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>225</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td>clk_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>100.000(MHz)</td>
<td>129.199(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>2.260</td>
<td>cmd_index_5_s0/Q</td>
<td>bit_loop_2_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>7.681</td>
</tr>
<tr>
<td>2</td>
<td>2.503</td>
<td>cmd_index_5_s0/Q</td>
<td>bit_loop_3_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.007</td>
<td>7.435</td>
</tr>
<tr>
<td>3</td>
<td>2.516</td>
<td>cmd_index_5_s0/Q</td>
<td>lcd_cs_r_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.041</td>
<td>7.381</td>
</tr>
<tr>
<td>4</td>
<td>2.643</td>
<td>cmd_index_5_s0/Q</td>
<td>bit_loop_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.296</td>
</tr>
<tr>
<td>5</td>
<td>2.673</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_2_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>7.268</td>
</tr>
<tr>
<td>6</td>
<td>2.744</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_6_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.036</td>
<td>7.159</td>
</tr>
<tr>
<td>7</td>
<td>2.780</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_0_s2/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.922</td>
</tr>
<tr>
<td>8</td>
<td>2.811</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_7_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.036</td>
<td>7.092</td>
</tr>
<tr>
<td>9</td>
<td>2.858</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_1_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.031</td>
<td>7.050</td>
</tr>
<tr>
<td>10</td>
<td>2.888</td>
<td>cmd_index_5_s0/Q</td>
<td>init_state_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.007</td>
<td>7.057</td>
</tr>
<tr>
<td>11</td>
<td>2.894</td>
<td>cmd_index_5_s0/Q</td>
<td>bit_loop_4_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.002</td>
<td>7.048</td>
</tr>
<tr>
<td>12</td>
<td>2.934</td>
<td>cmd_index_5_s0/Q</td>
<td>bit_loop_1_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.031</td>
<td>6.974</td>
</tr>
<tr>
<td>13</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_1_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>14</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_2_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>15</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_3_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>16</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_4_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>17</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_5_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>18</td>
<td>3.005</td>
<td>cmd_index_5_s0/Q</td>
<td>cmd_index_6_s0/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.696</td>
</tr>
<tr>
<td>19</td>
<td>3.037</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_5_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.031</td>
<td>6.871</td>
</tr>
<tr>
<td>20</td>
<td>3.246</td>
<td>cmd_index_5_s0/Q</td>
<td>init_state_2_s4/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.692</td>
</tr>
<tr>
<td>21</td>
<td>3.423</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_3_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.002</td>
<td>6.514</td>
</tr>
<tr>
<td>22</td>
<td>3.632</td>
<td>bit_loop_1_s2/Q</td>
<td>init_state_2_s4/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.031</td>
<td>6.100</td>
</tr>
<tr>
<td>23</td>
<td>3.704</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.235</td>
</tr>
<tr>
<td>24</td>
<td>3.723</td>
<td>cmd_index_5_s0/Q</td>
<td>spi_data_4_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>0.009</td>
<td>6.206</td>
</tr>
<tr>
<td>25</td>
<td>3.840</td>
<td>bit_loop_1_s2/Q</td>
<td>init_state_0_s2/CE</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>10.000</td>
<td>-0.037</td>
<td>5.898</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.362</td>
<td>clk_cnt_21_s1/Q</td>
<td>clk_cnt_21_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>2</td>
<td>0.362</td>
<td>clk_cnt_2_s1/Q</td>
<td>clk_cnt_2_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>3</td>
<td>0.362</td>
<td>clk_cnt_7_s1/Q</td>
<td>clk_cnt_7_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>4</td>
<td>0.362</td>
<td>clk_cnt_25_s1/Q</td>
<td>clk_cnt_25_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>5</td>
<td>0.362</td>
<td>clk_cnt_16_s1/Q</td>
<td>clk_cnt_16_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>6</td>
<td>0.362</td>
<td>pixel_cnt_0_s1/Q</td>
<td>pixel_cnt_0_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>7</td>
<td>0.362</td>
<td>clk_cnt_0_s1/Q</td>
<td>clk_cnt_0_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.364</td>
</tr>
<tr>
<td>8</td>
<td>0.366</td>
<td>clk_cnt_12_s1/Q</td>
<td>clk_cnt_12_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.367</td>
</tr>
<tr>
<td>9</td>
<td>0.426</td>
<td>bit_loop_0_s2/Q</td>
<td>bit_loop_0_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.427</td>
</tr>
<tr>
<td>10</td>
<td>0.430</td>
<td>clk_cnt_3_s1/Q</td>
<td>clk_cnt_3_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.431</td>
</tr>
<tr>
<td>11</td>
<td>0.448</td>
<td>clk_cnt_9_s1/Q</td>
<td>clk_cnt_9_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.449</td>
</tr>
<tr>
<td>12</td>
<td>0.448</td>
<td>clk_cnt_10_s1/Q</td>
<td>clk_cnt_10_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.449</td>
</tr>
<tr>
<td>13</td>
<td>0.460</td>
<td>clk_cnt_19_s1/Q</td>
<td>clk_cnt_19_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.461</td>
</tr>
<tr>
<td>14</td>
<td>0.476</td>
<td>clk_cnt_31_s1/Q</td>
<td>clk_cnt_31_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>15</td>
<td>0.476</td>
<td>clk_cnt_20_s1/Q</td>
<td>clk_cnt_20_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>16</td>
<td>0.476</td>
<td>clk_cnt_30_s1/Q</td>
<td>clk_cnt_30_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>17</td>
<td>0.476</td>
<td>clk_cnt_14_s1/Q</td>
<td>clk_cnt_14_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>18</td>
<td>0.476</td>
<td>clk_cnt_11_s1/Q</td>
<td>clk_cnt_11_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.478</td>
</tr>
<tr>
<td>19</td>
<td>0.480</td>
<td>clk_cnt_6_s1/Q</td>
<td>clk_cnt_6_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.481</td>
</tr>
<tr>
<td>20</td>
<td>0.480</td>
<td>clk_cnt_1_s1/Q</td>
<td>clk_cnt_1_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.481</td>
</tr>
<tr>
<td>21</td>
<td>0.480</td>
<td>bit_loop_2_s2/Q</td>
<td>bit_loop_2_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.481</td>
</tr>
<tr>
<td>22</td>
<td>0.484</td>
<td>init_state_1_s4/Q</td>
<td>init_state_1_s4/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.485</td>
</tr>
<tr>
<td>23</td>
<td>0.484</td>
<td>bit_loop_4_s2/Q</td>
<td>bit_loop_4_s2/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.485</td>
</tr>
<tr>
<td>24</td>
<td>0.485</td>
<td>clk_cnt_26_s1/Q</td>
<td>clk_cnt_26_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.486</td>
</tr>
<tr>
<td>25</td>
<td>0.487</td>
<td>cmd_index_0_s1/Q</td>
<td>cmd_index_0_s1/D</td>
<td>clk:[R]</td>
<td>clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.488</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>10000000000.000</td>
<td>4.824</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>cmd_index_6_s0</td>
</tr>
<tr>
<td>2</td>
<td>10000000000.000</td>
<td>4.824</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td>3</td>
<td>10000000000.000</td>
<td>4.824</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>cmd_index_3_s0</td>
</tr>
<tr>
<td>4</td>
<td>10000000000.000</td>
<td>4.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>pixel_cnt_15_s0</td>
</tr>
<tr>
<td>5</td>
<td>10000000000.000</td>
<td>4.833</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>pixel_cnt_7_s0</td>
</tr>
<tr>
<td>6</td>
<td>10000000000.000</td>
<td>4.825</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>clk_cnt_21_s1</td>
</tr>
<tr>
<td>7</td>
<td>10000000000.000</td>
<td>4.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>spi_data_1_s2</td>
</tr>
<tr>
<td>8</td>
<td>10000000000.000</td>
<td>4.822</td>
<td>-10000000000.000</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>pixel_cnt_0_s1</td>
</tr>
<tr>
<td>9</td>
<td>10000000000.000</td>
<td>4.829</td>
<td>-10000000000.000</td>
<td>High Pulse Width</td>
<td>clk</td>
<td>pixel_cnt_0_s1</td>
</tr>
<tr>
<td>10</td>
<td>10000000000.000</td>
<td>4.818</td>
<td>-10000000000.000</td>
<td>Low Pulse Width</td>
<td>clk</td>
<td>cmd_index_0_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.260</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.734</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.994</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_2_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.258</td>
<td>1.609</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C44[3][B]</td>
<td>n1452_s15/I0</td>
</tr>
<tr>
<td>6.736</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C44[3][B]</td>
<td style=" background: #97FFFF;">n1452_s15/F</td>
</tr>
<tr>
<td>7.782</td>
<td>1.046</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[2][B]</td>
<td>n1470_s10/I2</td>
</tr>
<tr>
<td>8.225</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C42[2][B]</td>
<td style=" background: #97FFFF;">n1470_s10/F</td>
</tr>
<tr>
<td>8.229</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>n1470_s9/I1</td>
</tr>
<tr>
<td>8.734</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td style=" background: #97FFFF;">n1470_s9/F</td>
</tr>
<tr>
<td>8.734</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_2_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.055</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>bit_loop_2_s2/CLK</td>
</tr>
<tr>
<td>10.994</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>bit_loop_2_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.176, 28.324%; route: 5.138, 66.896%; tC2Q: 0.367, 4.781%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.686%; route: 0.373, 35.314%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.503</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.488</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.991</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.629</td>
<td>1.980</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[3][B]</td>
<td>n1454_s20/I0</td>
</tr>
<tr>
<td>7.028</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C42[3][B]</td>
<td style=" background: #97FFFF;">n1454_s20/F</td>
</tr>
<tr>
<td>7.710</td>
<td>0.683</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[1][A]</td>
<td>n1468_s10/I3</td>
</tr>
<tr>
<td>8.206</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C43[1][A]</td>
<td style=" background: #97FFFF;">n1468_s10/F</td>
</tr>
<tr>
<td>8.210</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][A]</td>
<td>n1468_s9/I0</td>
</tr>
<tr>
<td>8.488</td>
<td>0.278</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C43[3][A]</td>
<td style=" background: #97FFFF;">n1468_s9/F</td>
</tr>
<tr>
<td>8.488</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C43[3][A]</td>
<td style=" font-weight:bold;">bit_loop_3_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.046</td>
<td>0.364</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][A]</td>
<td>bit_loop_3_s2/CLK</td>
</tr>
<tr>
<td>10.991</td>
<td>-0.055</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C43[3][A]</td>
<td>bit_loop_3_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.922, 25.855%; route: 5.146, 69.206%; tC2Q: 0.367, 4.939%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 65.242%; route: 0.364, 34.758%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.516</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.434</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.950</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>lcd_cs_r_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.744</td>
<td>1.094</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][B]</td>
<td>n1442_s23/I3</td>
</tr>
<tr>
<td>6.244</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][B]</td>
<td style=" background: #97FFFF;">n1442_s23/F</td>
</tr>
<tr>
<td>6.849</td>
<td>0.605</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C45[0][A]</td>
<td>n1466_s11/I3</td>
</tr>
<tr>
<td>7.101</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>R20C45[0][A]</td>
<td style=" background: #97FFFF;">n1466_s11/F</td>
</tr>
<tr>
<td>7.991</td>
<td>0.890</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C43[1][A]</td>
<td>n1446_s12/I0</td>
</tr>
<tr>
<td>8.434</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C43[1][A]</td>
<td style=" background: #97FFFF;">n1446_s12/F</td>
</tr>
<tr>
<td>8.434</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C43[1][A]</td>
<td style=" font-weight:bold;">lcd_cs_r_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.011</td>
<td>0.329</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C43[1][A]</td>
<td>lcd_cs_r_s2/CLK</td>
</tr>
<tr>
<td>10.950</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C43[1][A]</td>
<td>lcd_cs_r_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.041</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.945, 26.353%; route: 5.069, 68.672%; tC2Q: 0.367, 4.975%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 67.487%; route: 0.329, 32.513%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.643</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.349</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.991</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.552</td>
<td>0.902</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][B]</td>
<td>spi_data_0_s7/I1</td>
</tr>
<tr>
<td>5.950</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C43[3][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s7/F</td>
</tr>
<tr>
<td>6.477</td>
<td>0.527</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C43[0][B]</td>
<td>spi_data_0_s4/I3</td>
</tr>
<tr>
<td>6.982</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C43[0][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s4/F</td>
</tr>
<tr>
<td>7.844</td>
<td>0.862</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>n1474_s9/I2</td>
</tr>
<tr>
<td>8.349</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td style=" background: #97FFFF;">n1474_s9/F</td>
</tr>
<tr>
<td>8.349</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td style=" font-weight:bold;">bit_loop_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>bit_loop_0_s2/CLK</td>
</tr>
<tr>
<td>10.991</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>bit_loop_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.159, 29.589%; route: 4.770, 65.378%; tC2Q: 0.367, 5.033%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.673</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.321</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.994</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_2_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.629</td>
<td>1.980</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[3][B]</td>
<td>n1454_s20/I0</td>
</tr>
<tr>
<td>7.028</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C42[3][B]</td>
<td style=" background: #97FFFF;">n1454_s20/F</td>
</tr>
<tr>
<td>7.560</td>
<td>0.533</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][A]</td>
<td>n1460_s16/I3</td>
</tr>
<tr>
<td>8.066</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][A]</td>
<td style=" background: #97FFFF;">n1460_s16/F</td>
</tr>
<tr>
<td>8.069</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[1][A]</td>
<td>n1460_s13/I2</td>
</tr>
<tr>
<td>8.321</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C42[1][A]</td>
<td style=" background: #97FFFF;">n1460_s13/F</td>
</tr>
<tr>
<td>8.321</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[1][A]</td>
<td style=" font-weight:bold;">spi_data_2_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.055</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[1][A]</td>
<td>spi_data_2_s2/CLK</td>
</tr>
<tr>
<td>10.994</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C42[1][A]</td>
<td>spi_data_2_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.906, 26.218%; route: 4.996, 68.730%; tC2Q: 0.367, 5.052%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.686%; route: 0.373, 35.314%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.744</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_6_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.552</td>
<td>0.902</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][B]</td>
<td>spi_data_0_s7/I1</td>
</tr>
<tr>
<td>5.950</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C43[3][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s7/F</td>
</tr>
<tr>
<td>7.182</td>
<td>1.232</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C43[3][B]</td>
<td>n1452_s17/I2</td>
</tr>
<tr>
<td>7.660</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C43[3][B]</td>
<td style=" background: #97FFFF;">n1452_s17/F</td>
</tr>
<tr>
<td>7.814</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C44[3][A]</td>
<td>n1452_s13/I3</td>
</tr>
<tr>
<td>8.212</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C44[3][A]</td>
<td style=" background: #97FFFF;">n1452_s13/F</td>
</tr>
<tr>
<td>8.212</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C44[3][A]</td>
<td style=" font-weight:bold;">spi_data_6_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.017</td>
<td>0.334</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C44[3][A]</td>
<td>spi_data_6_s2/CLK</td>
</tr>
<tr>
<td>10.955</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C44[3][A]</td>
<td>spi_data_6_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.024, 28.277%; route: 4.768, 66.594%; tC2Q: 0.367, 5.129%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 67.129%; route: 0.334, 32.871%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.780</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.974</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.552</td>
<td>0.902</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][B]</td>
<td>spi_data_0_s7/I1</td>
</tr>
<tr>
<td>5.950</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C43[3][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s7/F</td>
</tr>
<tr>
<td>6.477</td>
<td>0.527</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C43[0][B]</td>
<td>spi_data_0_s4/I3</td>
</tr>
<tr>
<td>6.982</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C43[0][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s4/F</td>
</tr>
<tr>
<td>7.974</td>
<td>0.992</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td style=" font-weight:bold;">spi_data_0_s2/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td>spi_data_0_s2/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C44[0][B]</td>
<td>spi_data_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.654, 23.890%; route: 4.901, 70.804%; tC2Q: 0.367, 5.305%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.811</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.145</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.955</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_7_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.258</td>
<td>1.609</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C44[3][B]</td>
<td>n1452_s15/I0</td>
</tr>
<tr>
<td>6.736</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C44[3][B]</td>
<td style=" background: #97FFFF;">n1452_s15/F</td>
</tr>
<tr>
<td>7.394</td>
<td>0.658</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C42[1][B]</td>
<td>n1450_s16/I0</td>
</tr>
<tr>
<td>7.646</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C42[1][B]</td>
<td style=" background: #97FFFF;">n1450_s16/F</td>
</tr>
<tr>
<td>7.649</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C42[0][A]</td>
<td>n1450_s13/I3</td>
</tr>
<tr>
<td>8.145</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R15C42[0][A]</td>
<td style=" background: #97FFFF;">n1450_s13/F</td>
</tr>
<tr>
<td>8.145</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C42[0][A]</td>
<td style=" font-weight:bold;">spi_data_7_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.017</td>
<td>0.334</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C42[0][A]</td>
<td>spi_data_7_s2/CLK</td>
</tr>
<tr>
<td>10.955</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R15C42[0][A]</td>
<td>spi_data_7_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.036</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.975, 27.851%; route: 4.750, 66.971%; tC2Q: 0.367, 5.178%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 67.129%; route: 0.334, 32.871%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.858</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.103</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.961</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.629</td>
<td>1.980</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[3][B]</td>
<td>n1454_s20/I0</td>
</tr>
<tr>
<td>7.028</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C42[3][B]</td>
<td style=" background: #97FFFF;">n1454_s20/F</td>
</tr>
<tr>
<td>7.192</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C42[2][A]</td>
<td>n1462_s16/I3</td>
</tr>
<tr>
<td>7.697</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R17C42[2][A]</td>
<td style=" background: #97FFFF;">n1462_s16/F</td>
</tr>
<tr>
<td>7.851</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][A]</td>
<td>n1462_s13/I2</td>
</tr>
<tr>
<td>8.103</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][A]</td>
<td style=" background: #97FFFF;">n1462_s13/F</td>
</tr>
<tr>
<td>8.103</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][A]</td>
<td style=" font-weight:bold;">spi_data_1_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][A]</td>
<td>spi_data_1_s2/CLK</td>
</tr>
<tr>
<td>10.961</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C42[1][A]</td>
<td>spi_data_1_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.906, 27.030%; route: 4.777, 67.762%; tC2Q: 0.367, 5.209%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.888</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.110</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.998</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>init_state_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.744</td>
<td>1.094</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][B]</td>
<td>n1442_s23/I3</td>
</tr>
<tr>
<td>6.244</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][B]</td>
<td style=" background: #97FFFF;">n1442_s23/F</td>
</tr>
<tr>
<td>7.667</td>
<td>1.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td>n1442_s20/I3</td>
</tr>
<tr>
<td>8.110</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td style=" background: #97FFFF;">n1442_s20/F</td>
</tr>
<tr>
<td>8.110</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td style=" font-weight:bold;">init_state_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.059</td>
<td>0.377</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td>init_state_0_s2/CLK</td>
</tr>
<tr>
<td>10.998</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C49[0][A]</td>
<td>init_state_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.007</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.693, 23.993%; route: 4.997, 70.804%; tC2Q: 0.367, 5.203%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.429%; route: 0.377, 35.571%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.894</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.100</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.994</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.552</td>
<td>0.902</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[3][B]</td>
<td>spi_data_0_s7/I1</td>
</tr>
<tr>
<td>5.950</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R20C43[3][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s7/F</td>
</tr>
<tr>
<td>6.477</td>
<td>0.527</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C43[0][B]</td>
<td>spi_data_0_s4/I3</td>
</tr>
<tr>
<td>6.982</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R18C43[0][B]</td>
<td style=" background: #97FFFF;">spi_data_0_s4/F</td>
</tr>
<tr>
<td>7.658</td>
<td>0.676</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>n1466_s9/I1</td>
</tr>
<tr>
<td>8.100</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td style=" background: #97FFFF;">n1466_s9/F</td>
</tr>
<tr>
<td>8.100</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td style=" font-weight:bold;">bit_loop_4_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.055</td>
<td>0.373</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>bit_loop_4_s2/CLK</td>
</tr>
<tr>
<td>10.994</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>bit_loop_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.096, 29.746%; route: 4.584, 65.043%; tC2Q: 0.367, 5.210%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.686%; route: 0.373, 35.314%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.934</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.027</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.961</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.629</td>
<td>1.980</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[2][A]</td>
<td>n1472_s12/I1</td>
</tr>
<tr>
<td>7.072</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[2][A]</td>
<td style=" background: #97FFFF;">n1472_s12/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[2][B]</td>
<td>n1472_s10/I3</td>
</tr>
<tr>
<td>7.518</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[2][B]</td>
<td style=" background: #97FFFF;">n1472_s10/F</td>
</tr>
<tr>
<td>7.522</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td>n1472_s9/I0</td>
</tr>
<tr>
<td>8.027</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td style=" background: #97FFFF;">n1472_s9/F</td>
</tr>
<tr>
<td>8.027</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_1_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td>bit_loop_1_s2/CLK</td>
</tr>
<tr>
<td>10.961</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C42[0][B]</td>
<td>bit_loop_1_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.141, 30.695%; route: 4.466, 64.040%; tC2Q: 0.367, 5.265%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[0][A]</td>
<td style=" font-weight:bold;">cmd_index_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[0][A]</td>
<td>cmd_index_1_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[0][A]</td>
<td>cmd_index_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[0][B]</td>
<td style=" font-weight:bold;">cmd_index_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[0][B]</td>
<td>cmd_index_2_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[0][B]</td>
<td>cmd_index_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[1][A]</td>
<td style=" font-weight:bold;">cmd_index_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[1][A]</td>
<td>cmd_index_3_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[1][A]</td>
<td>cmd_index_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[1][B]</td>
<td style=" font-weight:bold;">cmd_index_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[1][B]</td>
<td>cmd_index_4_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[1][B]</td>
<td>cmd_index_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.005</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.749</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.566</td>
<td>0.157</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][A]</td>
<td>n1815_s9/I2</td>
</tr>
<tr>
<td>7.043</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][A]</td>
<td style=" background: #97FFFF;">n1815_s9/F</td>
</tr>
<tr>
<td>7.749</td>
<td>0.706</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][B]</td>
<td style=" font-weight:bold;">cmd_index_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][B]</td>
<td>cmd_index_6_s0/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C42[2][B]</td>
<td>cmd_index_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.705, 25.466%; route: 4.624, 69.050%; tC2Q: 0.367, 5.484%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.037</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.924</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.961</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_5_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>6.629</td>
<td>1.980</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[3][B]</td>
<td>n1454_s20/I0</td>
</tr>
<tr>
<td>7.028</td>
<td>0.398</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>R18C42[3][B]</td>
<td style=" background: #97FFFF;">n1454_s20/F</td>
</tr>
<tr>
<td>7.173</td>
<td>0.145</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][B]</td>
<td>n1454_s16/I3</td>
</tr>
<tr>
<td>7.425</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[1][B]</td>
<td style=" background: #97FFFF;">n1454_s16/F</td>
</tr>
<tr>
<td>7.428</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][A]</td>
<td>n1454_s13/I3</td>
</tr>
<tr>
<td>7.924</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][A]</td>
<td style=" background: #97FFFF;">n1454_s13/F</td>
</tr>
<tr>
<td>7.924</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][A]</td>
<td style=" font-weight:bold;">spi_data_5_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][A]</td>
<td>spi_data_5_s2/CLK</td>
</tr>
<tr>
<td>10.961</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C42[0][A]</td>
<td>spi_data_5_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.896, 27.593%; route: 4.608, 67.063%; tC2Q: 0.367, 5.344%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.246</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.745</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.991</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>init_state_2_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.744</td>
<td>1.094</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[3][B]</td>
<td>n1442_s23/I3</td>
</tr>
<tr>
<td>6.244</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R21C42[3][B]</td>
<td style=" background: #97FFFF;">n1442_s23/F</td>
</tr>
<tr>
<td>7.302</td>
<td>1.058</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>n1438_s25/I3</td>
</tr>
<tr>
<td>7.745</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td style=" background: #97FFFF;">n1438_s25/F</td>
</tr>
<tr>
<td>7.745</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td style=" font-weight:bold;">init_state_2_s4/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>init_state_2_s4/CLK</td>
</tr>
<tr>
<td>10.991</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>init_state_2_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.693, 25.300%; route: 4.632, 69.213%; tC2Q: 0.367, 5.487%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.423</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.566</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.989</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C42[3][B]</td>
<td>n1458_s20/I2</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R23C42[3][B]</td>
<td style=" background: #97FFFF;">n1458_s20/F</td>
</tr>
<tr>
<td>6.562</td>
<td>0.154</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[1][B]</td>
<td>n1458_s14/I3</td>
</tr>
<tr>
<td>7.067</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C42[1][B]</td>
<td style=" background: #97FFFF;">n1458_s14/F</td>
</tr>
<tr>
<td>7.071</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[0][A]</td>
<td>n1458_s13/I0</td>
</tr>
<tr>
<td>7.566</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C42[0][A]</td>
<td style=" background: #97FFFF;">n1458_s13/F</td>
</tr>
<tr>
<td>7.566</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[0][A]</td>
<td style=" font-weight:bold;">spi_data_3_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.050</td>
<td>0.368</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[0][A]</td>
<td>spi_data_3_s2/CLK</td>
</tr>
<tr>
<td>10.989</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C42[0][A]</td>
<td>spi_data_3_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.002</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.228, 34.211%; route: 3.918, 60.151%; tC2Q: 0.367, 5.637%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.981%; route: 0.368, 35.019%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.632</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.122</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.754</td>
</tr>
<tr>
<td class="label">From</td>
<td>bit_loop_1_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>init_state_2_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td>bit_loop_1_s2/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_1_s2/Q</td>
</tr>
<tr>
<td>2.214</td>
<td>0.824</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[0][B]</td>
<td>n1815_s3/I1</td>
</tr>
<tr>
<td>2.709</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>28</td>
<td>R20C43[0][B]</td>
<td style=" background: #97FFFF;">n1815_s3/F</td>
</tr>
<tr>
<td>3.582</td>
<td>0.872</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][A]</td>
<td>n1815_s1/I1</td>
</tr>
<tr>
<td>3.834</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][A]</td>
<td style=" background: #97FFFF;">n1815_s1/F</td>
</tr>
<tr>
<td>5.835</td>
<td>2.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[1][B]</td>
<td>init_state_2_s7/I1</td>
</tr>
<tr>
<td>6.278</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C49[1][B]</td>
<td style=" background: #97FFFF;">init_state_2_s7/F</td>
</tr>
<tr>
<td>6.282</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[3][A]</td>
<td>init_state_2_s6/I0</td>
</tr>
<tr>
<td>6.782</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C49[3][A]</td>
<td style=" background: #97FFFF;">init_state_2_s6/F</td>
</tr>
<tr>
<td>7.122</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td style=" font-weight:bold;">init_state_2_s4/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>init_state_2_s4/CLK</td>
</tr>
<tr>
<td>10.754</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C48[2][A]</td>
<td>init_state_2_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.031</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.691, 27.720%; route: 4.042, 66.260%; tC2Q: 0.367, 6.020%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.704</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.288</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.991</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.931</td>
<td>1.282</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C42[3][B]</td>
<td>n1815_s8/I0</td>
</tr>
<tr>
<td>6.408</td>
<td>0.478</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C42[3][B]</td>
<td style=" background: #97FFFF;">n1815_s8/F</td>
</tr>
<tr>
<td>6.783</td>
<td>0.374</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td>n1464_s26/I2</td>
</tr>
<tr>
<td>7.288</td>
<td>0.505</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td style=" background: #97FFFF;">n1464_s26/F</td>
</tr>
<tr>
<td>7.288</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td style=" font-weight:bold;">spi_data_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[0][B]</td>
<td>spi_data_0_s2/CLK</td>
</tr>
<tr>
<td>10.991</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C44[0][B]</td>
<td>spi_data_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.733, 27.791%; route: 4.135, 66.320%; tC2Q: 0.367, 5.889%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.723</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.259</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.983</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>spi_data_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C42[2][A]</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
<tr>
<td>1.420</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R21C42[2][A]</td>
<td style=" font-weight:bold;">cmd_index_5_s0/Q</td>
</tr>
<tr>
<td>2.475</td>
<td>1.055</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][B]</td>
<td>n1815_s6/I0</td>
</tr>
<tr>
<td>2.970</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][B]</td>
<td style=" background: #97FFFF;">n1815_s6/F</td>
</tr>
<tr>
<td>4.395</td>
<td>1.424</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C48[3][A]</td>
<td>n1815_s4/I3</td>
</tr>
<tr>
<td>4.649</td>
<td>0.254</td>
<td>tINS</td>
<td>RR</td>
<td>12</td>
<td>R22C48[3][A]</td>
<td style=" background: #97FFFF;">n1815_s4/F</td>
</tr>
<tr>
<td>5.687</td>
<td>1.038</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[1][B]</td>
<td>n1456_s17/I0</td>
</tr>
<tr>
<td>6.130</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C43[1][B]</td>
<td style=" background: #97FFFF;">n1456_s17/F</td>
</tr>
<tr>
<td>6.134</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[2][A]</td>
<td>n1456_s15/I0</td>
</tr>
<tr>
<td>6.629</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C43[2][A]</td>
<td style=" background: #97FFFF;">n1456_s15/F</td>
</tr>
<tr>
<td>6.764</td>
<td>0.134</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>n1456_s13/I2</td>
</tr>
<tr>
<td>7.259</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" background: #97FFFF;">n1456_s13/F</td>
</tr>
<tr>
<td>7.259</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td style=" font-weight:bold;">spi_data_4_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.044</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>spi_data_4_s2/CLK</td>
</tr>
<tr>
<td>10.983</td>
<td>-0.061</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C43[0][A]</td>
<td>spi_data_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.009</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 64.833%; route: 0.370, 35.167%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.184, 35.189%; route: 3.655, 58.894%; tC2Q: 0.367, 5.916%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 65.392%; route: 0.361, 34.608%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.840</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.920</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>bit_loop_1_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>init_state_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C42[0][B]</td>
<td>bit_loop_1_s2/CLK</td>
</tr>
<tr>
<td>1.389</td>
<td>0.367</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R18C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_1_s2/Q</td>
</tr>
<tr>
<td>2.214</td>
<td>0.824</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C43[0][B]</td>
<td>n1815_s3/I1</td>
</tr>
<tr>
<td>2.709</td>
<td>0.496</td>
<td>tINS</td>
<td>RR</td>
<td>28</td>
<td>R20C43[0][B]</td>
<td style=" background: #97FFFF;">n1815_s3/F</td>
</tr>
<tr>
<td>3.582</td>
<td>0.872</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C45[0][A]</td>
<td>n1815_s1/I1</td>
</tr>
<tr>
<td>3.834</td>
<td>0.252</td>
<td>tINS</td>
<td>RR</td>
<td>6</td>
<td>R18C45[0][A]</td>
<td style=" background: #97FFFF;">n1815_s1/F</td>
</tr>
<tr>
<td>5.835</td>
<td>2.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[1][B]</td>
<td>init_state_2_s7/I1</td>
</tr>
<tr>
<td>6.278</td>
<td>0.443</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R22C49[1][B]</td>
<td style=" background: #97FFFF;">init_state_2_s7/F</td>
</tr>
<tr>
<td>6.282</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[3][A]</td>
<td>init_state_2_s6/I0</td>
</tr>
<tr>
<td>6.782</td>
<td>0.500</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C49[3][A]</td>
<td style=" background: #97FFFF;">init_state_2_s6/F</td>
</tr>
<tr>
<td>6.920</td>
<td>0.138</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td style=" font-weight:bold;">init_state_0_s2/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>11.059</td>
<td>0.377</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][A]</td>
<td>init_state_0_s2/CLK</td>
</tr>
<tr>
<td>10.760</td>
<td>-0.299</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C49[0][A]</td>
<td>init_state_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.037</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.683, 66.774%; route: 0.340, 33.226%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.691, 28.667%; route: 3.840, 65.107%; tC2Q: 0.367, 6.226%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.683, 64.429%; route: 0.377, 35.571%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.211</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.849</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_21_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_21_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][A]</td>
<td>clk_cnt_21_s1/CLK</td>
</tr>
<tr>
<td>1.020</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R17C49[1][A]</td>
<td style=" font-weight:bold;">clk_cnt_21_s1/Q</td>
</tr>
<tr>
<td>1.028</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][A]</td>
<td>n1392_s7/I2</td>
</tr>
<tr>
<td>1.211</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C49[1][A]</td>
<td style=" background: #97FFFF;">n1392_s7/F</td>
</tr>
<tr>
<td>1.211</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C49[1][A]</td>
<td style=" font-weight:bold;">clk_cnt_21_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][A]</td>
<td>clk_cnt_21_s1/CLK</td>
</tr>
<tr>
<td>0.849</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C49[1][A]</td>
<td>clk_cnt_21_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>clk_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>6</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_2_s1/Q</td>
</tr>
<tr>
<td>1.024</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>n1430_s7/I3</td>
</tr>
<tr>
<td>1.208</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" background: #97FFFF;">n1430_s7/F</td>
</tr>
<tr>
<td>1.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>clk_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C48[0][A]</td>
<td>clk_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>clk_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R18C50[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_7_s1/Q</td>
</tr>
<tr>
<td>1.024</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>n1420_s7/I2</td>
</tr>
<tr>
<td>1.208</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td style=" background: #97FFFF;">n1420_s7/F</td>
</tr>
<tr>
<td>1.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_7_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>clk_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C50[0][A]</td>
<td>clk_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.208</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_25_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_25_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>clk_cnt_25_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C50[1][A]</td>
<td style=" font-weight:bold;">clk_cnt_25_s1/Q</td>
</tr>
<tr>
<td>1.024</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>n1384_s7/I3</td>
</tr>
<tr>
<td>1.208</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td style=" background: #97FFFF;">n1384_s7/F</td>
</tr>
<tr>
<td>1.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td style=" font-weight:bold;">clk_cnt_25_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>clk_cnt_25_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C50[1][A]</td>
<td>clk_cnt_25_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.204</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.841</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_16_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_16_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C48[0][A]</td>
<td>clk_cnt_16_s1/CLK</td>
</tr>
<tr>
<td>1.013</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R15C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_16_s1/Q</td>
</tr>
<tr>
<td>1.020</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C48[0][A]</td>
<td>n1402_s7/I3</td>
</tr>
<tr>
<td>1.204</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R15C48[0][A]</td>
<td style=" background: #97FFFF;">n1402_s7/F</td>
</tr>
<tr>
<td>1.204</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R15C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_16_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.840</td>
<td>0.164</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C48[0][A]</td>
<td>clk_cnt_16_s1/CLK</td>
</tr>
<tr>
<td>0.841</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C48[0][A]</td>
<td>clk_cnt_16_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.426%; route: 0.164, 19.574%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.426%; route: 0.164, 19.574%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.207</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>pixel_cnt_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>pixel_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.016</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">pixel_cnt_0_s1/Q</td>
</tr>
<tr>
<td>1.023</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>n1226_s3/I0</td>
</tr>
<tr>
<td>1.207</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" background: #97FFFF;">n1226_s3/F</td>
</tr>
<tr>
<td>1.207</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td style=" font-weight:bold;">pixel_cnt_0_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>0.844</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C44[0][A]</td>
<td>pixel_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.362</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.232</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.870</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>clk_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.041</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R21C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_0_s1/Q</td>
</tr>
<tr>
<td>1.049</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>n1434_s8/I0</td>
</tr>
<tr>
<td>1.232</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td style=" background: #97FFFF;">n1434_s8/F</td>
</tr>
<tr>
<td>1.232</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_0_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>clk_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>0.870</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C48[0][A]</td>
<td>clk_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.495%; route: 0.007, 1.980%; tC2Q: 0.173, 47.525%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.238</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_12_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_12_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[0][A]</td>
<td>clk_cnt_12_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R20C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_12_s1/Q</td>
</tr>
<tr>
<td>1.054</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[0][A]</td>
<td>n1410_s7/I3</td>
</tr>
<tr>
<td>1.238</td>
<td>0.184</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C48[0][A]</td>
<td style=" background: #97FFFF;">n1410_s7/F</td>
</tr>
<tr>
<td>1.238</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C48[0][A]</td>
<td style=" font-weight:bold;">clk_cnt_12_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[0][A]</td>
<td>clk_cnt_12_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C48[0][A]</td>
<td>clk_cnt_12_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 50.000%; route: 0.011, 2.941%; tC2Q: 0.173, 47.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.426</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.870</td>
</tr>
<tr>
<td class="label">From</td>
<td>bit_loop_0_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>bit_loop_0_s2/CLK</td>
</tr>
<tr>
<td>1.041</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>10</td>
<td>R21C44[2][A]</td>
<td style=" font-weight:bold;">bit_loop_0_s2/Q</td>
</tr>
<tr>
<td>1.049</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>n1474_s9/I3</td>
</tr>
<tr>
<td>1.296</td>
<td>0.247</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td style=" background: #97FFFF;">n1474_s9/F</td>
</tr>
<tr>
<td>1.296</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td style=" font-weight:bold;">bit_loop_0_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.869</td>
<td>0.193</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>bit_loop_0_s2/CLK</td>
</tr>
<tr>
<td>0.870</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R21C44[2][A]</td>
<td>bit_loop_0_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.247, 57.865%; route: 0.007, 1.685%; tC2Q: 0.173, 40.449%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.760%; route: 0.193, 22.240%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.430</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.275</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[2][A]</td>
<td>clk_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R18C50[2][A]</td>
<td style=" font-weight:bold;">clk_cnt_3_s1/Q</td>
</tr>
<tr>
<td>1.028</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[2][A]</td>
<td>n1428_s7/I2</td>
</tr>
<tr>
<td>1.275</td>
<td>0.247</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C50[2][A]</td>
<td style=" background: #97FFFF;">n1428_s7/F</td>
</tr>
<tr>
<td>1.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C50[2][A]</td>
<td style=" font-weight:bold;">clk_cnt_3_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[2][A]</td>
<td>clk_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C50[2][A]</td>
<td>clk_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.247, 57.382%; route: 0.011, 2.507%; tC2Q: 0.173, 40.111%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.320</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_9_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[0][B]</td>
<td>clk_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>1.040</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C50[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_9_s1/Q</td>
</tr>
<tr>
<td>1.136</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[0][B]</td>
<td>n1416_s7/I3</td>
</tr>
<tr>
<td>1.320</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C50[0][B]</td>
<td style=" background: #97FFFF;">n1416_s7/F</td>
</tr>
<tr>
<td>1.320</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_9_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[0][B]</td>
<td>clk_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C50[0][B]</td>
<td>clk_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 40.909%; route: 0.096, 21.390%; tC2Q: 0.169, 37.701%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.448</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.320</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_10_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_10_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[1][B]</td>
<td>clk_cnt_10_s1/CLK</td>
</tr>
<tr>
<td>1.040</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R20C48[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_10_s1/Q</td>
</tr>
<tr>
<td>1.136</td>
<td>0.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C48[1][B]</td>
<td>n1414_s7/I2</td>
</tr>
<tr>
<td>1.320</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R20C48[1][B]</td>
<td style=" background: #97FFFF;">n1414_s7/F</td>
</tr>
<tr>
<td>1.320</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C48[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_10_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[1][B]</td>
<td>clk_cnt_10_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C48[1][B]</td>
<td>clk_cnt_10_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 40.909%; route: 0.096, 21.390%; tC2Q: 0.169, 37.701%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.460</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.309</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.849</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_19_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_19_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][B]</td>
<td>clk_cnt_19_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.169</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C49[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_19_s1/Q</td>
</tr>
<tr>
<td>1.125</td>
<td>0.108</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C49[0][B]</td>
<td>n1396_s7/I3</td>
</tr>
<tr>
<td>1.309</td>
<td>0.184</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R17C49[0][B]</td>
<td style=" background: #97FFFF;">n1396_s7/F</td>
</tr>
<tr>
<td>1.309</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C49[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_19_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[0][B]</td>
<td>clk_cnt_19_s1/CLK</td>
</tr>
<tr>
<td>0.849</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C49[0][B]</td>
<td>clk_cnt_19_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.184, 39.844%; route: 0.108, 23.438%; tC2Q: 0.169, 36.719%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.319</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_31_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_31_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td>clk_cnt_31_s1/CLK</td>
</tr>
<tr>
<td>1.014</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R16C48[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_31_s1/Q</td>
</tr>
<tr>
<td>1.021</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td>n1372_s7/I2</td>
</tr>
<tr>
<td>1.319</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td style=" background: #97FFFF;">n1372_s7/F</td>
</tr>
<tr>
<td>1.319</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_31_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[0][B]</td>
<td>clk_cnt_31_s1/CLK</td>
</tr>
<tr>
<td>0.843</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C48[0][B]</td>
<td>clk_cnt_31_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.325</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.849</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_20_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_20_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][B]</td>
<td>clk_cnt_20_s1/CLK</td>
</tr>
<tr>
<td>1.020</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R17C49[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_20_s1/Q</td>
</tr>
<tr>
<td>1.028</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][B]</td>
<td>n1394_s7/I2</td>
</tr>
<tr>
<td>1.325</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C49[1][B]</td>
<td style=" background: #97FFFF;">n1394_s7/F</td>
</tr>
<tr>
<td>1.325</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C49[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_20_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.848</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C49[1][B]</td>
<td>clk_cnt_20_s1/CLK</td>
</tr>
<tr>
<td>0.849</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C49[1][B]</td>
<td>clk_cnt_20_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.686%; route: 0.172, 20.314%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.319</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.843</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_30_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_30_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>clk_cnt_30_s1/CLK</td>
</tr>
<tr>
<td>1.014</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R16C48[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_30_s1/Q</td>
</tr>
<tr>
<td>1.021</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>n1374_s8/I2</td>
</tr>
<tr>
<td>1.319</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td style=" background: #97FFFF;">n1374_s8/F</td>
</tr>
<tr>
<td>1.319</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_30_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.841</td>
<td>0.166</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>clk_cnt_30_s1/CLK</td>
</tr>
<tr>
<td>0.843</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R16C48[1][B]</td>
<td>clk_cnt_30_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.283%; route: 0.166, 19.717%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.321</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.844</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_14_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_14_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[0][B]</td>
<td>clk_cnt_14_s1/CLK</td>
</tr>
<tr>
<td>1.016</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>5</td>
<td>R17C48[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_14_s1/Q</td>
</tr>
<tr>
<td>1.023</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[0][B]</td>
<td>n1406_s8/I1</td>
</tr>
<tr>
<td>1.321</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R17C48[0][B]</td>
<td style=" background: #97FFFF;">n1406_s8/F</td>
</tr>
<tr>
<td>1.321</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C48[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_14_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C48[0][B]</td>
<td>clk_cnt_14_s1/CLK</td>
</tr>
<tr>
<td>0.844</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C48[0][B]</td>
<td>clk_cnt_14_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 80.140%; route: 0.167, 19.860%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.476</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.348</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_11_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_11_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][B]</td>
<td>clk_cnt_11_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R20C50[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_11_s1/Q</td>
</tr>
<tr>
<td>1.051</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][B]</td>
<td>n1412_s7/I1</td>
</tr>
<tr>
<td>1.348</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C50[1][B]</td>
<td style=" background: #97FFFF;">n1412_s7/F</td>
</tr>
<tr>
<td>1.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C50[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_11_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C50[1][B]</td>
<td>clk_cnt_11_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C50[1][B]</td>
<td>clk_cnt_11_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 62.312%; route: 0.007, 1.508%; tC2Q: 0.173, 36.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.480</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.357</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.877</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][B]</td>
<td>clk_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>1.048</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R20C49[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_6_s1/Q</td>
</tr>
<tr>
<td>1.059</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][B]</td>
<td>n1422_s7/I3</td>
</tr>
<tr>
<td>1.357</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C49[1][B]</td>
<td style=" background: #97FFFF;">n1422_s7/F</td>
</tr>
<tr>
<td>1.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C49[1][B]</td>
<td style=" font-weight:bold;">clk_cnt_6_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.876</td>
<td>0.200</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C49[1][B]</td>
<td>clk_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>0.877</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C49[1][B]</td>
<td>clk_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 61.845%; route: 0.011, 2.244%; tC2Q: 0.173, 35.910%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.147%; route: 0.200, 22.853%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.480</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.326</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.846</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>clk_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>1.017</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>7</td>
<td>R18C50[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_1_s1/Q</td>
</tr>
<tr>
<td>1.028</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>n1432_s7/I2</td>
</tr>
<tr>
<td>1.326</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td style=" background: #97FFFF;">n1432_s7/F</td>
</tr>
<tr>
<td>1.326</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td style=" font-weight:bold;">clk_cnt_1_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.844</td>
<td>0.169</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>clk_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>0.846</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C50[0][B]</td>
<td>clk_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 61.845%; route: 0.011, 2.244%; tC2Q: 0.173, 35.910%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 79.998%; route: 0.169, 20.002%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.480</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.352</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>bit_loop_2_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_2_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>bit_loop_2_s2/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R20C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_2_s2/Q</td>
</tr>
<tr>
<td>1.054</td>
<td>0.011</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>n1470_s9/I3</td>
</tr>
<tr>
<td>1.352</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td style=" background: #97FFFF;">n1470_s9/F</td>
</tr>
<tr>
<td>1.352</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td style=" font-weight:bold;">bit_loop_2_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>bit_loop_2_s2/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C42[0][B]</td>
<td>bit_loop_2_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 61.845%; route: 0.011, 2.244%; tC2Q: 0.173, 35.910%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.356</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.873</td>
</tr>
<tr>
<td class="label">From</td>
<td>init_state_1_s4</td>
</tr>
<tr>
<td class="label">To</td>
<td>init_state_1_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][B]</td>
<td>init_state_1_s4/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>16</td>
<td>R22C49[0][B]</td>
<td style=" font-weight:bold;">init_state_1_s4/Q</td>
</tr>
<tr>
<td>1.059</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][B]</td>
<td>n1440_s21/I3</td>
</tr>
<tr>
<td>1.356</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C49[0][B]</td>
<td style=" background: #97FFFF;">n1440_s21/F</td>
</tr>
<tr>
<td>1.356</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C49[0][B]</td>
<td style=" font-weight:bold;">init_state_1_s4/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C49[0][B]</td>
<td>init_state_1_s4/CLK</td>
</tr>
<tr>
<td>0.873</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C49[0][B]</td>
<td>init_state_1_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.519%; route: 0.196, 22.481%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 61.386%; route: 0.014, 2.970%; tC2Q: 0.173, 35.644%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.519%; route: 0.196, 22.481%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.484</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.356</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>bit_loop_4_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>bit_loop_4_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>bit_loop_4_s2/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>7</td>
<td>R20C44[0][B]</td>
<td style=" font-weight:bold;">bit_loop_4_s2/Q</td>
</tr>
<tr>
<td>1.058</td>
<td>0.014</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>n1466_s9/I2</td>
</tr>
<tr>
<td>1.356</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td style=" background: #97FFFF;">n1466_s9/F</td>
</tr>
<tr>
<td>1.356</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td style=" font-weight:bold;">bit_loop_4_s2/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>bit_loop_4_s2/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C44[0][B]</td>
<td>bit_loop_4_s2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 61.386%; route: 0.014, 2.970%; tC2Q: 0.173, 35.644%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.485</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.357</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.872</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_cnt_26_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_cnt_26_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[2][B]</td>
<td>clk_cnt_26_s1/CLK</td>
</tr>
<tr>
<td>1.044</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R20C48[2][B]</td>
<td style=" font-weight:bold;">clk_cnt_26_s1/Q</td>
</tr>
<tr>
<td>1.051</td>
<td>0.007</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[2][B]</td>
<td>n1382_s7/I2</td>
</tr>
<tr>
<td>1.357</td>
<td>0.306</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R20C48[2][B]</td>
<td style=" background: #97FFFF;">n1382_s7/F</td>
</tr>
<tr>
<td>1.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C48[2][B]</td>
<td style=" font-weight:bold;">clk_cnt_26_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.871</td>
<td>0.195</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C48[2][B]</td>
<td>clk_cnt_26_s1/CLK</td>
</tr>
<tr>
<td>0.872</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C48[2][B]</td>
<td>clk_cnt_26_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.306, 62.963%; route: 0.007, 1.481%; tC2Q: 0.173, 35.556%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 77.572%; route: 0.195, 22.428%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.487</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.350</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.863</td>
</tr>
<tr>
<td class="label">From</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>cmd_index_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>1.035</td>
<td>0.173</td>
<td>tC2Q</td>
<td>RR</td>
<td>50</td>
<td>R22C43[0][B]</td>
<td style=" font-weight:bold;">cmd_index_0_s1/Q</td>
</tr>
<tr>
<td>1.053</td>
<td>0.018</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>n1124_s3/I0</td>
</tr>
<tr>
<td>1.350</td>
<td>0.298</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td style=" background: #97FFFF;">n1124_s3/F</td>
</tr>
<tr>
<td>1.350</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td style=" font-weight:bold;">cmd_index_0_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOB12[A]</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>75</td>
<td>IOB12[A]</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
<tr>
<td>0.863</td>
<td>0.001</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R22C43[0][B]</td>
<td>cmd_index_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.298, 60.934%; route: 0.018, 3.686%; tC2Q: 0.173, 35.381%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.675, 78.382%; route: 0.186, 21.618%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.824</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cmd_index_6_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>cmd_index_6_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.877</td>
<td>0.199</td>
<td>tNET</td>
<td>FF</td>
<td>cmd_index_6_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.824</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cmd_index_5_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.877</td>
<td>0.199</td>
<td>tNET</td>
<td>FF</td>
<td>cmd_index_5_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.824</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cmd_index_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.053</td>
<td>0.370</td>
<td>tNET</td>
<td>RR</td>
<td>cmd_index_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.877</td>
<td>0.199</td>
<td>tNET</td>
<td>FF</td>
<td>cmd_index_3_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>pixel_cnt_15_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.018</td>
<td>0.336</td>
<td>tNET</td>
<td>RR</td>
<td>pixel_cnt_15_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.847</td>
<td>0.170</td>
<td>tNET</td>
<td>FF</td>
<td>pixel_cnt_15_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.833</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>pixel_cnt_7_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.010</td>
<td>0.327</td>
<td>tNET</td>
<td>RR</td>
<td>pixel_cnt_7_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.842</td>
<td>0.165</td>
<td>tNET</td>
<td>FF</td>
<td>pixel_cnt_7_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.825</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>clk_cnt_21_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.029</td>
<td>0.347</td>
<td>tNET</td>
<td>RR</td>
<td>clk_cnt_21_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.854</td>
<td>0.176</td>
<td>tNET</td>
<td>FF</td>
<td>clk_cnt_21_s1/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>spi_data_1_s2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.022</td>
<td>0.340</td>
<td>tNET</td>
<td>RR</td>
<td>spi_data_1_s2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.851</td>
<td>0.173</td>
<td>tNET</td>
<td>FF</td>
<td>spi_data_1_s2/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.822</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>pixel_cnt_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>6.021</td>
<td>0.333</td>
<td>tNET</td>
<td>FF</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.843</td>
<td>0.167</td>
<td>tNET</td>
<td>RR</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.829</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>High Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>pixel_cnt_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>1.020</td>
<td>0.338</td>
<td>tNET</td>
<td>RR</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.677</td>
<td>0.678</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>5.849</td>
<td>0.172</td>
<td>tNET</td>
<td>FF</td>
<td>pixel_cnt_0_s1/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>10000000000.000</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.818</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>-10000000000.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cmd_index_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>6.044</td>
<td>0.356</td>
<td>tNET</td>
<td>FF</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.675</td>
<td>0.675</td>
<td>tINS</td>
<td>RR</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.862</td>
<td>0.186</td>
<td>tNET</td>
<td>RR</td>
<td>cmd_index_0_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>75</td>
<td>lcd_clk_d</td>
<td>2.260</td>
<td>0.382</td>
</tr>
<tr>
<td>50</td>
<td>cmd_index[0]</td>
<td>3.959</td>
<td>1.264</td>
</tr>
<tr>
<td>50</td>
<td>cmd_index[2]</td>
<td>3.250</td>
<td>1.955</td>
</tr>
<tr>
<td>48</td>
<td>cmd_index[3]</td>
<td>3.651</td>
<td>1.283</td>
</tr>
<tr>
<td>47</td>
<td>cmd_index[1]</td>
<td>3.678</td>
<td>1.769</td>
</tr>
<tr>
<td>35</td>
<td>n1374_11</td>
<td>6.966</td>
<td>0.982</td>
</tr>
<tr>
<td>29</td>
<td>init_state_2_13</td>
<td>4.423</td>
<td>1.199</td>
</tr>
<tr>
<td>28</td>
<td>cmd_index[4]</td>
<td>3.239</td>
<td>1.430</td>
</tr>
<tr>
<td>28</td>
<td>n1815_6</td>
<td>3.614</td>
<td>1.270</td>
</tr>
<tr>
<td>20</td>
<td>bit_loop[3]</td>
<td>4.688</td>
<td>1.098</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R20C43</td>
<td>44.44%</td>
</tr>
<tr>
<td>R20C44</td>
<td>44.44%</td>
</tr>
<tr>
<td>R21C42</td>
<td>43.06%</td>
</tr>
<tr>
<td>R21C43</td>
<td>43.06%</td>
</tr>
<tr>
<td>R18C44</td>
<td>40.28%</td>
</tr>
<tr>
<td>R18C43</td>
<td>34.72%</td>
</tr>
<tr>
<td>R22C43</td>
<td>34.72%</td>
</tr>
<tr>
<td>R21C44</td>
<td>34.72%</td>
</tr>
<tr>
<td>R20C48</td>
<td>34.72%</td>
</tr>
<tr>
<td>R16C43</td>
<td>33.33%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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